1. Field of the Invention
The present invention relates to a method of forming a barrier film and to a method of forming the wiring structure and electrodes of semiconductor device having a barrier film.
2. Description of the Related Art
Generally, in the manufacture of a semiconductor integrated device such as a semiconductor integrated circuit, various processes such as film-formation, oxidative diffusion and etching are repeatedly applied onto a semiconductor wafer to form a large number of transistor, capacitors and resistance, and thereafter these elements are connected with each other through wiring patterns. Furthermore, in order to meet persistent demands for a high-performance integrated circuit as well as for a multi-functional integrated circuit, it is now required to further reduce the line width of wiring patterns and to further enhance the integration of the semiconductor elements. Moreover, a multi-layered structure has come to be employed in which circuits themselves are stacked one another with an insulating layer being interposed therebetween.
Since the electric resistance of the wirings or connecting portions is caused to increase due to a decrease in cross-sectional area thereof under the aforementioned circumstances, there is an increasing trend to employ copper, as a wiring material, in place of aluminum which has been generally employed up to date due to the facts that copper is highly resistant to electromigration and relatively low in resistivity even though copper cannot be so easily formed into a film as compared with aluminum.
As for the gate electrode to be employed in a transistor element, the polycide layer structure consisting of a doped polysilicon and a molybdenum silicide or tungsten silicide layer and titanium silicide layer stacked on the doped polysilicon layer has been generally employed. However, with a view to further promote the operation speed and to further lower the resistivity of gate electrode in conformity with the recent trend of further enhancing the integration of semiconductor devices by reducing the line width of wiring to not more than 0.1 μm and of further miniaturizing the semiconductor chip, there have been studied various measures, e.g. measures to dispose a poly-metal gate structure which is replaced the upper silicide layer of the polycide-layered gate electrode by a single metal layer, for example, a tungsten layer, or measures to direct dispose a metal layer on the surface of gate oxide film of a metal-gate structure where even the polysilicon layer is omitted.
Incidentally, copper and tungsten are known to be highly active as they are employed singly, so that they can be easily reacted with other kinds of element. For example, metal copper is high in diffusion coefficient, so that it can be easily diffused into a layer of Si or SiO2, thereby generating the segregation thereof and crystal defects (copper is allowed to react with Si to form copper silicide). As a result, not only the electric resistance of the gate electrode is caused to increase, but also the exfoliation thereof (the exfoliation from the mixing layer of copper) is caused to easily occur.
On the other hand, when the upper layer of gate electrode of polycide-layered structure is constituted by a metal tungsten film, the silicon atoms in a doped polysilicon layer constituting the lower layer of the polycide-layered gate electrode are allowed to interdiffuse and react with the tungsten of the metal tungsten film, thereby giving rise to the formation of tungsten silicide exhibiting a high electric resistance.
It is conceivable, for the purpose of preventing the reaction between the metal copper and the metal tungsten, to employ a barrier metal such as TiN (titanium nitride) which has been conventionally employed. However, since this TiN layer has high resistivity, and is also not so effective as a diffusion barrier to copper and tungsten, this TiN layer cannot be employed as a preferable barrier metal. In particular, the barrier properties of this TiN layer to Cu are very poor.
Furthermore, in order to meet the recent demands for further enhancing the integration, multilayer structure and operation speed of semiconductor integrated circuit, it is desired, when the gate electrode for example is taken up as one example, to make each gate electrode layer thinner so as to lower the electric resistance thereof and to make aspect ratio higher on the occasion of etching work of the gate electrode.
However, as the thinning of polysilicon film, for example, constituting a gate electrode is further enhanced, there will be raised a problem that the polysilicon film is high resistivity. It is also conceivable in this case to interpose a conventionally known TiN film as a barrier metal between the tungsten film and the polysilicon layer. In this case however, a barrier metal such as TiN film is high electric resistance and is unsatisfactory for use as a diffusion barrier for copper (because the barrier film is also inevitably made thinner).
Further, with respect to the problem of the disposal of residual gas in a film-forming step, it is proposed in U.S. Pat. No. 6,015,590 that in order to effectively form a thin film, at least 99% of the residual gas should be discharged. According to this U.S. Patent, the apparatus thereof is designed such that not only the capacity thereof but also the cross-section of piping become as minimum as possible so as to achieve an effective evacuation. Furthermore, the apparatus according to this U.S. Patent is also designed in such a manner that a dead space which makes it difficult to perform the purging of gas can be prevented from being generated. Additionally, according to this U.S. Patent, since the capacity of the chamber is designed to become as minimum as possible, the gas flow therein would be inevitably caused to spread as substantially a planer flow to thereby form a “flat” flow pattern. However, according to this U.S. Patent, since the design of apparatus is extremely restricted for the purpose of effectively perform the deposition of thin film, it is difficult to actually employ it in combination with a conventional CVD chamber.